Integrated circuit (IC) fabrication processes include, among other things, lithographic processes that transfer predetermined IC layout patterns provided on masks to various layers of materials for forming different elements on a substrate. In some applications, the exposure resolution of a lithographic process is limited by many factors such as the light source used and the precision of the lenses, etc. In some semiconductor fabrication processes, double or multiple exposures performed in conjunction with two or more masks for the same layer of material are used to provide an equivalent exposure resolution finer than that can be reached by performing a single exposure. One example double-exposure technology is referred to as double patterning technology (DPT), where layout patterns are assigned to two different masks for two consecutively performed lithographic processes for the same layer of material. However, misalignment between the two different masks (measurable by the relative displacement of the resulting patterns on the wafer) exists, which leads to degraded performance or even failure of the resulting IC.